Search - DDS Verilog

[VHDL-FPGA-Verilog] verilog实现FSK

Description: 用verilog语言，采用DDS技术实现的FSK
Platform: | Size: 4009917 | Author: yfvictoria | Hits:

[Windows Develop] ram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1024 | Author: 杨艳 | Hits:

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3072 | Author: 陈榧 | Hits:

[Embeded-SCM Develop] DDSsignalgen

Description: dds信号发生器-dds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, FSK
Platform: | Size: 3331072 | Author: appolo | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[Windows CE] DDSFPGA_cylone

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
Platform: | Size: 637952 | Author: 苏纳 | Hits:

[Software Engineering] ddsbyvhdl

Description: 摘要：介绍了基于可编程逻辑器件CPLD和直接数字频率合成技术（DDS）的三相多波形函数发生器的基本原理，并在此基础上给出了基于CPLD的各模块设计方法及其VHDL源程序-Abstract : Based on the CPLD and direct digital frequency synthesis (DDS) of a three-phase multi-function waveform Generator to the basic principles and on this basis given the CPLD based on the module design and VHDL source
Platform: | Size: 47104 | Author: 陈鑫 | Hits:

[Other Embeded program] DDS

Description: Verilog语言实现基于DDS技术的余弦信号发生器，输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
Platform: | Size: 4096 | Author: 柏承建 | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS数字式频率合成器利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
Platform: | Size: 382976 | Author: | Hits:

[SCM] DDS

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square wave three, and can sweep. Can be set by keyboard operation frequency parameters and select the waveform type and control operation. Consists of two parts, " C" folder, is used to running on the microcontroller in the 51 C language program, " Verilog" folder, is written in Verilog FPGA program.
Platform: | Size: 433152 | Author: 王金 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
Platform: | Size: 16772096 | Author: allen-haha | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
Platform: | Size: 5120 | Author: 张君 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
Platform: | Size: 6281216 | Author: 王凡 | Hits:

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[VHDL-FPGA-Verilog] verilog实现FSK

[Windows Develop] ram

[Communication] DDS_VERILOG

[Embeded-SCM Develop] DDSsignalgen

[VHDL-FPGA-Verilog] DDS_Power

[Windows CE] DDSFPGA_cylone

[Software Engineering] ddsbyvhdl

[Other Embeded program] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[SCM] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS-in-Verilog

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] 四通道DDS信号发生器

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS -changed

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